28.
(Continued)
Step 2. Identify input SM+A (R+I) +NE.
a. SM+A (R+I) +NE--this signifies a three-input OR gate.
Step 3. Connect the output of the OR gate to the input of the NAND gate as shown
below.
Step 4. Identify input SM.
a. S M--this signifies a two-input AND gate.
b. Input S is INHIBITED.
Step 5. Connect the output of the AND gate to the input of the OR gate as shown below.
Step 6. Identify input A (R+I).
a. A (R+l) --this signifies a two-input AND gate.
Step 7. Connect the output of the AND gate to the input of the OR gate as shown below.